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--- en:research:sr:manuel:reference-manuel:subsystem [2007/02/23 11:33]
brunner
+++ en:research:sr:manuel:reference-manuel:subsystem [2007/02/23 11:40]
brunner
@@ Line 40: / Line 40: @@
 <latex>f_adc=100MHz</latex>,
 which fullfills the above equation.
 ===== Reception-chain =====
-<wikionly>{{figure.png|The whole chain and the most important part of it}
+<figure>en:research:sr:manuel:rx-chain|Reception-chain|cap:Reception-chain</figure>
-\end{figure}}</wikionly><htmlonly><a id="cap:Reception-chain"></a></htmlonly>
+<figure>en:research:sr:manuel:ddc|The whole chain and the most important part of it|cap:DDC-chain</figure>
-<texit>
-\begin{figure}[ht]
-\subfigure[Whole Reception chain]{
-\includegraphics[width=0.45\textwidth]{Figures/rx-chain.eps}
-\label{cap:Reception-chain}
-}
-\hfill
-\subfigure[DDC-chain]{
-\includegraphics[width=0.45\textwidth]{Figures/ddc.eps}
-\label{cap:DDC-chain}}
-\caption{The whole chain and the most important part of it}
-\end{figure}
-</texit>
 The different parameters of fig.<ref>cap:Reception-chain</ref> and
@@ Line 67: / Line 56: @@
 <ldt>f_adc</ldt><ldd>[1-100]MHz, the sampling frequency of the ADC.</ldd>
 <ldt>fi_rx</ldt><ldd>[1-500]MHz, the intermediate frequency. Every frequency above <latex>\frac{f_ adc}{2}</latex> will be attenuated due to the sinc of the ADC.</ldd>
-<ldt>fs_rx</ldt><ldd>[0-$\frac{f_ adc}{8}$]MHz, the final sampling frequency (the DDC does down-sampling). Contrary to f_adc, fs_rx is measured in complex samples.</ldd>
+<ldt>fs_rx</ldt><ldd>[0-<latex>\frac{f_ adc}{8}</latex>]MHz, the final sampling frequency (the DDC does down-sampling). Contrary to f_adc, fs_rx is measured in complex samples.</ldd>
 <ldt>w_rx</ldt><ldd>[0.08-0.75], the portion of the final sampling frequency fs_rx which is not cut off by the DDC filters.</ldd>
 </ldl>
-\begin{comment}
+<texit> \begin{comment}
 How is the bandwith related to fs_rx? Is it 0.08-0.75 or 0.16 - 1.5?
-\end{comment}
+\end{comment} </texit>
 <ldl>
-<ldt>sig_type</ldt><ldd>\{ SIG_COMPLEX_ICS, SIG_S16 \} for FPGA_DEFAULT\\ \{ SIG_COMPLEX_S16 \} for FPGA_S16</ldd>
+<ldt>sig_type</ldt><ldd>{ SIG_COMPLEX_ICS, SIG_S16 } for FPGA_DEFAULT\\ { SIG_COMPLEX_S16 } for FPGA_S16</ldd>
 </ldl>