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| - | Master thesis project: 2008-2009 | + | Master thesis project: |
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| Generation of a noise signal with user-defined spectrum mask for spurious signals emulation in wireless transmissions. | Generation of a noise signal with user-defined spectrum mask for spurious signals emulation in wireless transmissions. | ||
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| **Background:**\\ | **Background:**\\ | ||
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| Another much more simple way to achieve similar work and results is to generate a pseudo-random signal having a spectrum mask representative of all impairment signals. This can be achieved in digital domain by appropriate FIR filtering of some white Gaussian noise. | Another much more simple way to achieve similar work and results is to generate a pseudo-random signal having a spectrum mask representative of all impairment signals. This can be achieved in digital domain by appropriate FIR filtering of some white Gaussian noise. | ||
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| **Objective:**\\ | **Objective:**\\ | ||
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| A third step is to implement a real-time parametrizable FIR filter on an hardware FPGA-based (programmable component) platform and to verify correct operation for various template curves. | A third step is to implement a real-time parametrizable FIR filter on an hardware FPGA-based (programmable component) platform and to verify correct operation for various template curves. | ||
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| **Deliverables:**\\ | **Deliverables:**\\ | ||
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| - VHDL module for real-time filters implementation.\\ | - VHDL module for real-time filters implementation.\\ | ||
| - Final project report (diploma report). | - Final project report (diploma report). | ||
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| **Organization:**\\ | **Organization:**\\ | ||
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| ** Comment:**\\ | ** Comment:**\\ | ||
| - | This project constitutes a very good pre-professional experience through the skills it will enable to enrich (FPGA/ASIC development and PC user-interface development are commonly and highly requested by industry) and through the fact that student(s) will collaborate to a real industrial project.\\ | + | This project constitutes a very good pre-professional experience through the skills it will enable to enrich (FPGA/ASIC development and PC user-interface development are commonly and highly requested by industry) and through the fact that student(s) will collaborate to a real industrial project. |
| This project can be achieved by 1 student or can be merged with the “RadioStress” project in order to constitute a 2 students team. | This project can be achieved by 1 student or can be merged with the “RadioStress” project in order to constitute a 2 students team. | ||
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| **Prerequisites:**\\ | **Prerequisites:**\\ | ||
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| - VHDL language (preferable but not mandatory) | - VHDL language (preferable but not mandatory) | ||
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| **Supervisor:**\\ | **Supervisor:**\\ | ||
| - | Jean-François Csomo | + | Jean-François Csomo, DreamCom |
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| **Professor:**\\ | **Professor:**\\ | ||
| Prof. Bixio Rimoldi, tel: 32679, office: INR 111, bixio.rimoldi@epfl.ch | Prof. Bixio Rimoldi, tel: 32679, office: INR 111, bixio.rimoldi@epfl.ch | ||
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| - | [[en:projects:2008-2009:mtp|back to master thesis projects menu]] | + | [[en:projects:2007-2008:mtp|back to master thesis projects menu]] |