====== Subsystems ======

The software-radio has a reception and a transmission part.
Each one of these has its specialities and quirks.
Here I list the names used in programming, the restrictions and how they come
across.
Only the reception-part is treated in this document, as the transmission-part
is quite simple.


===== Nyquist =====

It is very important to understand the implication of Nyquists theorem for this
reception-chain.
Nyquist wrote that the sampling-frequency must be twice the bandwith of the
signal to sample.
He also described the aliasing that happens if you sample a signal that is out
of this bound.
For the reception-part of the software-radio, we rely on this aliasing to
capture a signal at an intermediate frequency of 70MHz using a
sampling-frequency of 100MHz.
In a most general way, given the parameters:

<ldl>
<ldt>fi_rx</ldt><ldd>the intermediate frequency</ldd>
<ldt>wi_rx</ldt><ldd>the intermediate used bandwith</ldd>
<ldt>f_adc</ldt><ldd>the sampling-frequency of the analog-to-digital converter</ldd>
</ldl>

then f_adc must be chosen so that
<latex>$\frac{f_ adc}{2}N\notin\left[fi_ rx-\frac{wi_ rx}{2}, fi_ rx+\frac{wi_
rx}{2}\right]$</latex>
is fulfilled. Else we get an overlapping of the aliased signal and we loose
information.

For the software-radio,
<latex>fi_rx=70MHz</latex>,
<latex>wi_rx=20MHz</latex>,
<latex>f_adc=100MHz</latex>,
which fullfills the above equation.



===== Reception-chain =====

<figure>en:research:sr:manuel:rx-chain|Reception-chain|cap:Reception-chain</figure>
<figure>en:research:sr:manuel:ddc|The whole chain and the most important part of it|cap:DDC-chain</figure>

The different parameters of fig.<ref>cap:Reception-chain</ref> and
fig.<ref>cap:DDC-chain</ref>, their boundaries, and a short description:

<ldl>
<ldt>f_rf</ldt><ldd>[2300..2500]MHz, the transmission-frequency</ldd>
<ldt>attn_rx</ldt><ldd>[0-41]dB, the attenuation of the Rx-chain (0 gives stronges output, 41 gives weakest)</ldd>
<ldt>f_adc</ldt><ldd>[1-100]MHz, the sampling frequency of the ADC.</ldd>
<ldt>fi_rx</ldt><ldd>[1-500]MHz, the intermediate frequency. Every frequency above <latex>\frac{f_ adc}{2}</latex> will be attenuated due to the sinc of the ADC.</ldd>
<ldt>fs_rx</ldt><ldd>[0-<latex>\frac{f_ adc}{8}</latex>]MHz, the final sampling frequency (the DDC does down-sampling). Contrary to f_adc, fs_rx is measured in complex samples.</ldd>
<ldt>w_rx</ldt><ldd>[0.08-0.75], the portion of the final sampling frequency fs_rx which is not cut off by the DDC filters.</ldd>
</ldl>

<texit> \begin{comment}
How is the bandwith related to fs_rx? Is it 0.08-0.75 or 0.16 - 1.5?
\end{comment} </texit>

<ldl>
<ldt>sig_type</ldt><ldd>{ SIG_COMPLEX_ICS, SIG_S16 } for FPGA_DEFAULT\\ { SIG_COMPLEX_S16 } for FPGA_S16</ldd>
</ldl>

===== More detail =====

The final sampling frequency is limited by the use of the DDCs in the card.
A simplified structure of the DDCs can be seen in fig.<ref>cap:DDC-chain</ref>.
Due to internal limitations, the smallest useable decimation factor of the DDCs
is 8, and the highest is 4096.
For more detail, see the Graychip-documentation on page 11, 3.4.2 and
references.


==== w_rx ====

This parameter is also dependant on the DDC-chips. In fig.<ref>cap:DDC-chain</ref>
this is simplified by a //Filtering// block.
The DDC itself does implement this filtering with two filters, called
//cfir// and //ffir//. The exact nature of these
filters is subject to a subsequent work and thus only pre-calculated filters
have been used. This is why the bandwith can
only be one of {0.085, 0.17, 0.34, 0.40, 0.50, 0.75}.

Another point here: the filters in //filters.c// are defined for twice this
bandwith. This is because of the internal
workings of the DDCs and can only be understood through a thorough study of the
Graychip-documentation, see also the document about the DDC by Ignace.

==== sig_type ====

The signal-types are defined for the software-radio and can be chosen to be one
of the following. The choice of the signal-type influences also whether the
DDCs are used or not.

<ldl>
<ldt>SIG_COMPLEX_ICS</ldt><ldd>is the standard mode of the ICS-card. In this mode, DDCs are enabled and the signal is outputted in baseband.</ldd>
<ldt>SIG_S16</ldt><ldd>bypasses the DDCs and transfers the direct output of the ADCs. This has been tested with one ADC only. It is useful for processing high-bandwith signals.</ldd>
<ldt>SIG_COMPLEX_S16</ldt><ldd>is only possible with a re-programmed FPGA on the ICS-cards. DDCs are enabled, only one channel is transmitted, but not in the SIG_COMPLEX_ICS format that takes 128bits per sample, but in a more simple SIG_COMPLEX_S16 format, that only takes 32bits per complex sample, thus allowing 4 times more storage.</ldd>
</ldl>